1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits that use metal-oxide-semiconductor (MOS) transistors, has been increasing. With the increase in the degree of integration, MOS transistors used in the integrated circuits have been miniaturized to the nanometer scale. With such a miniaturization of MOS transistors, there may be a problem in that it becomes difficult to reduce a leakage current and the area occupied by circuits is not easily decreased from the viewpoint of ensuring a required amount of current. In order to address this problem, a surrounding gate transistor (SGT) has been proposed in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and the gate surrounds a pillar-shaped semiconductor layer (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
For example, Japanese Unexamined Patent Application Publication No. 2015-188115 has proposed that a silicide is formed in a portion on the outside of an insulating film that is formed, as a sidewall, on a side wall of a gate electrode, the portion being a part of a planar semiconductor layer under a pillar-shaped semiconductor layer. With this structure, the resistance of a diffusion layer formed in the planar semiconductor layer under the pillar-shaped semiconductor layer is reduced. However, only the diffusion layer is disposed between a lower portion of the pillar-shaped semiconductor layer and the outside of the insulating film that is formed, as the sidewall, on the side wall of the gate electrode, and thus a reduction in the parasitic resistance has not been realized.